In very large scale integrated (VLSI) circuit devices, several wiring or metal layers are required to connect together the active or passive elements in a VLSI semiconductor chip. The interconnection structure consists of thin conductive lines separated by insulation (silicon dioxide) in one layer or level and connected to elements of the semiconductor chip or to a similar layer in another level. Vias or studs extend through the insulation and can be connected to contacts associated with the elements of the semiconductor chip. Connections between levels or layers and between layers and the elements of the semiconductor chip are then made. Conventional ultra-large scale integrated (ULSI) circuit devices can include five or more layers.
The interconnection structure associated with VLSI and ULSI circuits is similar to a transmission line in that there is a propagation delay of the signals being transmitted in these wiring layers. The delay is referred to as RC delay because it generally relates to the resistance (R) of the material of the wire and the capacitance (C) between adjacent wires.
With the trend of higher and higher levels of integration in integrated circuits (ICs), the space or gap (e.g., the thickness between the conductive lines or layers) is becoming extremely narrow, such as about 0.5 microns and smaller. Such a narrow space or gap between conductive lines increases the capacitance and places greater demands on the insulating properties of the insulation between such conductive lines. Capacitance (C) is the product of dielectric constant (k) of the insulating material times the area (A) of the opposing faces of the conductive line divided by the distance (D) between the conductive lines ##EQU1##
With a decrease in distance (D), the capacitance (C) increases. Since signal delay of signals transmitted on the conductive line is controlled by the RC constant, an increase in capacitance (C) degrades the performance of the integrated circuit.
Thus, it is desirable to replace traditional silicon dioxide (SiO.sub.2) insulative materials in multi-level interconnect devices with dielectric materials having low dielectric constants (hereinafter referred to as low-k dielectric materials). A disadvantage to using low-k dielectric materials is that traditional photoresist removal processes (e.g., ashing and solvent cleaning) causes degradation of most low-k dielectric materials. For example, photoresist removal on low-k dielectric materials, such as, hydrogen silsesquioxanes (HSQ), spin on glass (SOG), benzocyclobutine (BCB), etc., causes the dielectric constant (k) to increase. Furthermore, the conventional solvent cleaning of the integrated circuit after the ashing process typically causes further degradation of low-k dielectrics and causes increases in dielectric constant k.
Thus, there is a need and desire for a method of producing integrated circuits, including VLSI and ULSI circuits, that maintains the integrity of low-k dielectric materials during the ashing and solvent cleaning process associated with photoresist removal. Further, there is a need and desire for a method of producing integrated circuit devices that uses a non-oxygen gas (O.sub.2) or trace O.sub.2 forming gas plasma process that creates a protective surface layer and removes photoresist with a relatively high ashing rate. Further still, there is a need and desire for a method of producing an integrated circuit device that uses a high temperature and high vacuum degassing process to remove trace amounts of photoresist and eliminates moisture on the surface of the integrated circuit device while preserving the integrity of the low-k dielectric material.